Abstract
Deep neural networks (DNNs) are widely applied to artificial intelligence applications, achieving promising performance at the cost of massive computation, large power consumption, and high latency. Diverse solutions have been proposed to cope with the challenge of latency and power consumption, including light-weight neural networks and efficient hardware accelerators. Moreover, research on quantization reduces the cost of computation and shows the error resiliency of DNNs. To improve the latency and power efficiency of hardware accelerators by exploiting the error resiliency, we propose an application-specific optimization method for the automatic design of approximate multipliers for DNNs. The proposed method optimizes an approximate multiplier by minimizing the error according to the probability distributions extracted from DNNs. By applying the optimized approximate multiplier to a DNN, we obtain 1.60%, 15.32%, and 20.19% higher accuracies than the best reproduced approximate multiplier on the widely used MNIST, FashionMNIST, and CIFAR-10 datasets, respectively, with 12.17% smaller area, 23.38% less power consumption, and 16.53% lower latency. Compared with an exact multiplier, the optimized multiplier reduces the area, power consumption, and latency by 36.88%, 52.45%, and 26.63%, respectively. Applied to FPGA-based and ASIC-based DNN accelerator modules, our approximate multiplier obtains low LUT utilization and small area respectively with competitive max frequency and power consumption, which shows the effectiveness of the proposed method in reducing the hardware cost of DNN accelerators.
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URL
https://arxiv.org/abs/2201.08022
