Abstract
Edge computing is a promising solution for handling high-dimensional, multispectral analog data from sensors and IoT devices for applications such as autonomous drones. However, edge devices' limited storage and computing resources make it challenging to perform complex predictive modeling at the edge. Compute-in-memory (CiM) has emerged as a principal paradigm to minimize energy for deep learning-based inference at the edge. Nevertheless, integrating storage and processing complicates memory cells and/or memory peripherals, essentially trading off area efficiency for energy efficiency. This paper proposes a novel solution to improve area efficiency in deep learning inference tasks. The proposed method employs two key strategies. Firstly, a Frequency domain learning approach uses binarized Walsh-Hadamard Transforms, reducing the necessary parameters for DNN (by 87% in MobileNetV2) and enabling compute-in-SRAM, which better utilizes parallelism during inference. Secondly, a memory-immersed collaborative digitization method is described among CiM arrays to reduce the area overheads of conventional ADCs. This facilitates more CiM arrays in limited footprint designs, leading to better parallelism and reduced external memory accesses. Different networking configurations are explored, where Flash, SA, and their hybrid digitization steps can be implemented using the memory-immersed scheme. The results are demonstrated using a 65 nm CMOS test chip, exhibiting significant area and energy savings compared to a 40 nm-node 5-bit SAR ADC and 5-bit Flash ADC. By processing analog data more efficiently, it is possible to selectively retain valuable data from sensors and alleviate the challenges posed by the analog data deluge.
Abstract (translated)
边缘计算是一个有前途的解决方案,用于处理来自传感器和物联网设备的高度多维模拟数据,例如自主无人机的应用。然而,边缘设备有限的存储和计算资源使得在边缘进行复杂的预测建模具有挑战性。计算在内存(CiM)已经成为最小化基于深度学习的推理所需的能量的主要范式,CiM方法使用二进制瓦氏哈姆变换,减少了深度学习模型所需的参数(在 MobileNetV2中减少87%),并允许计算在内存中执行,这更好地利用了并行性在推理期间。第二,描述了在 CiM数组中的内存沉浸式协作数字重构方法,以减少传统ADC的面积 overhead。这使得在相对较小 footprint 的设计中更多 CiM数组实现,导致更好的并行性和减少外部内存访问。不同网络配置被探索,其中 Flash、SA 和它们的混合数字重构步骤可以使用内存沉浸式方案实现。结果使用65纳米 CMOS测试芯片演示了,与40纳米节点5位SAR ADC 和5位 Flash ADC相比,表现出显著的面积和能源节省。通过更高效地处理模拟数据,可以选择保留传感器中的有价值的数据,减轻模拟数据倾泻带来的挑战。
URL
https://arxiv.org/abs/2309.11048
