Abstract
Spiking Neural Networks (SNNs) are promising biologically plausible models of computation which utilize a spiking binary activation function similar to that of biological neurons. SNNs are well positioned to process spatiotemporal data, and are advantageous in ultra-low power and real-time processing. Despite a large body of work on conventional artificial neural network accelerators, much less attention has been given to efficient SNN hardware accelerator design. In particular, SNNs exhibit inherent unstructured spatial and temporal firing sparsity, an opportunity yet to be fully explored for great hardware processing efficiency. In this work, we propose a novel systolic-array SNN accelerator architecture, called SpikeX, to take on the challenges and opportunities stemming from unstructured sparsity while taking into account the unique characteristics of spike-based computation. By developing an efficient dataflow targeting expensive multi-bit weight data movements, SpikeX reduces memory access and increases data sharing and hardware utilization for computations spanning across both time and space, thereby significantly improving energy efficiency and inference latency. Furthermore, recognizing the importance of SNN network and hardware co-design, we develop a co-optimization methodology facilitating not only hardware-aware SNN training but also hardware accelerator architecture search, allowing joint network weight parameter optimization and accelerator architectural reconfiguration. This end-to-end network/accelerator co-design approach offers a significant reduction of 15.1x-150.87x in energy-delay-product(EDP) without comprising model accuracy.
Abstract (translated)
脉冲神经网络（SNNs）是一种具有生物学合理性的计算模型，其利用类似于生物神经元的尖峰二进制激活函数。SNNs非常适合处理时空数据，并在超低功耗和实时处理方面表现出优势。尽管传统的人工神经网络加速器已有大量研究工作，但针对高效SNN硬件加速器设计的关注较少。特别是，SNN们展示了固有的、无结构的空间和时间放电稀疏性，这是一个尚未被完全探索的用于大幅提升硬件处理效率的机会。 在这项工作中，我们提出了一种新颖的用于应对未结构化稀疏性的挑战与机遇的脉冲神经网络加速器架构，称为SpikeX。该架构考虑了基于尖峰计算的独特特性，通过开发一种高效的数据流来减少昂贵的多比特权重数据移动，从而减少了内存访问并增加了跨时间和空间的数据共享和硬件利用率，这显著提高了能效和推理延迟。 此外，考虑到脉冲神经网络与硬件协同设计的重要性，我们还发展了一种协同优化方法论。该方法不仅支持硬件感知的SNN训练，而且还支持硬件加速器架构搜索，从而实现联合网络权重参数优化和加速器结构重构。这种端到端的网络/加速器协同设计方法能够在不牺牲模型精度的前提下，将能源延迟产品（EDP）降低15.1倍至150.87倍。 通过这种方式，SpikeX为脉冲神经网络硬件加速提供了新的视角，并展示了在实际应用中实现高效计算的巨大潜力。
URL
https://arxiv.org/abs/2505.12292
