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HOMI: Ultra-Fast EdgeAI platform for Event Cameras

2025-08-18 05:47:48
Shankaranarayanan H, Satyapreet Singh Yadav, Adithya Krishna, Ajay Vikram P, Mahesh Mehendale, Chetan Singh Thakur

Abstract

Event cameras offer significant advantages for edge robotics applications due to their asynchronous operation and sparse, event-driven output, making them well-suited for tasks requiring fast and efficient closed-loop control, such as gesture-based human-robot interaction. Despite this potential, existing event processing solutions remain limited, often lacking complete end-to-end implementations, exhibiting high latency, and insufficiently exploiting event data sparsity. In this paper, we present HOMI, an ultra-low latency, end-to-end edge AI platform comprising a Prophesee IMX636 event sensor chip with an Xilinx Zynq UltraScale+MPSoC FPGA chip, deploying an in-house developed AI accelerator. We have developed hardware-optimized pre-processing pipelines supporting both constant-time and constant-event modes for histogram accumulation, linear and exponential time surfaces. Our general-purpose implementation caters to both accuracy-driven and low-latency applications. HOMI achieves 94% accuracy on the DVS Gesture dataset as a use case when configured for high accuracy operation and provides a throughput of 1000 fps for low-latency configuration. The hardware-optimised pipeline maintains a compact memory footprint and utilises only 33% of the available LUT resources on the FPGA, leaving ample headroom for further latency reduction, model parallelisation, multi-task deployments, or integration of more complex architectures.

Abstract (translated)

事件相机在边缘机器人应用中提供了显著的优势,这是因为它们的异步操作和稀疏、事件驱动的输出特性非常适合需要快速且高效闭环控制的任务,如基于手势的人机交互。尽管存在这些潜力,现有的事件处理解决方案仍然有限,通常缺乏完整的端到端实现,表现出高延迟,并未能充分挖掘事件数据的稀疏性。 在这篇论文中,我们介绍了HOMI,这是一个超低延时、端到端边缘AI平台,集成了Prophesee IMX636事件传感器芯片与Xilinx Zynq UltraScale+ MPSoC FPGA芯片,并部署了一个内部开发的人工智能加速器。我们开发了硬件优化的预处理流水线,支持常数时间模式和常数事件模式下的直方图累积、以及线性和指数时间表面。我们的通用实现同时适用于以准确性驱动的应用程序和低延迟应用程序。 当配置为高精度操作时,HOMI在DVS手势数据集上实现了94%的准确率,并且在低延迟配置下提供了每秒1000帧的吞吐量。硬件优化的流水线保持了紧凑的记忆占用,并仅使用FPGA上可用LUT资源的33%,为未来的延时减少、模型并行化、多任务部署或更复杂架构的集成留出了充足的空间。

URL

https://arxiv.org/abs/2508.12637

PDF

https://arxiv.org/pdf/2508.12637.pdf


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