Abstract
Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations. This paper presents a systolic array architecture incorporating novel exact and approximate processing elements (PEs), designed using energy-efficient positive partial product and negative partial product cells, termed as PPC and NPPC, respectively. The proposed 8-bit exact and approximate PE designs are employed in a 8x8 systolic array, which achieves a energy savings of 22% and 32%, respectively, compared to the existing design. To demonstrate their effectiveness, the proposed PEs are integrated into a systolic array (SA) for Discrete Cosine Transform (DCT) computation, achieving high output quality with a PSNR of 38.21,dB. Furthermore, in an edge detection application using convolution, the approximate PE achieves a PSNR of 30.45,dB. These results highlight the potential of the proposed design to deliver significant energy efficiency while maintaining competitive output quality, making it well-suited for error-resilient image and vision processing applications.
Abstract (translated)
深度神经网络（DNN）需要高效的矩阵乘法引擎来进行复杂的计算。本文提出了一种采用新型精确和近似处理单元（PEs）的 systolic 数组架构，这些单元使用节能的正部分积和负部分积细胞设计，分别称为 PPC 和 NPPC。提出的 8 位精确和近似 PE 设计被应用于一个 8x8 的 systolic 数组，在与现有设计相比时，前者在能量节省方面达到了22%和32%。 为了证明其有效性，所提出的 PEs 被集成到用于离散余弦变换（DCT）计算的 systolic 数组中，实现了高达 38.21 dB 的 PSNR 输出质量。此外，在使用卷积进行边缘检测的应用中，近似 PE 实现了 30.45 dB 的 PSNR。 这些结果突显了所提出的架构在保持竞争力输出质量的同时能够实现显著的能源效率，并且该设计非常适合于具有错误容忍能力的图像和视觉处理应用。
URL
https://arxiv.org/abs/2509.00778
