Abstract
The exponential increase in complex IPs within modern SoCs, driven by Moore's Law, has created a pressing need for fast and accurate hardware-software power-performance analysis. Traditional performance simulators (such as cycle accurate simulators) are often too slow to simulate full benchmarks within a reasonable timeframe; require considerable effort for development, maintenance, and extensions; and are prone to errors, making pre-silicon performance projections and competitive analysis increasingly challenging. Prior attempts in addressing this challenge using machine learning fall short as they are either slow, inaccurate or unable to predict the performance of full benchmarks. To address these limitations, we present PAI, the first technique to accurately predict full benchmark performance without relying on detailed simulation or instruction-wise encoding. At the heart of PAI is a hierarchical Long Short Term Memory (LSTM)-based model that takes a trace of microarchitecture independent features from a program execution and predicts performance metrics. We present the detailed design, implementation and evaluation of PAI. Our initial experiments showed that PAI can achieve an average IPC prediction error of 9.35% for SPEC CPU 2017 benchmark suite while taking only 2 min 57 sec for the entire suite. This prediction error is comparable to prior state-of-the-art techniques while requiring 3 orders of magnitude less time.
Abstract (translated)
摩尔定律推动下现代SoC中复杂IP数量的指数级增长，催生了快速精准的软硬件功耗性能分析需求。传统性能模拟器（如周期精确模拟器）往往因模拟完整基准测试耗时过长而难以在合理时间内完成；其开发、维护与扩展需要大量投入，且容易产生误差，使得硅前性能预测与竞品分析愈发困难。此前尝试用机器学习解决该挑战的方法均存在不足：要么速度慢，要么精度低，要么无法预测完整基准测试性能。为突破这些限制，本文提出PAI——首个无需依赖详细模拟或指令级编码即可准确预测完整基准测试性能的技术。PAI的核心是一个基于分层长短期记忆网络（LSTM）的模型，该模型通过提取程序执行中与微架构无关的特征轨迹来预测性能指标。本文详细阐述了PAI的设计、实现与评估过程。初步实验表明，PAI在SPEC CPU 2017基准测试套件上平均IPC预测误差仅为9.35%，而处理整个套件仅需2分57秒。该预测误差与现有顶尖技术相当，但耗时减少了三个数量级。
URL
https://arxiv.org/abs/2603.19330
